Modeling the Effects of Systematic Process Variation on Circuit Performance

As technology scales, understanding semiconductor manufacturing variation becomes essential to effectively design high performance circuits. Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise. Conventional circuit techniques typically represent the interconnect and device parameter variations as random variables. However, recent studies have shown that strong spatial pattern dependencies exist, especially when considering interconnect variation in chemical mechanical polishing (CMP) processes. Therefore, the total variation can be separated into systematic and random components, where a significant portion of the variation can be modeled based on layout characteristics. Modeling the systematic components of different variation sources and implementing these effects in circuit simulation are key to reduce design uncertainty and maximize circuit performance. This thesis presents a methodology to incorporate systematic pattern dependent interconnect and device variation models for use with circuit extraction and simulation tools. The methodology is applicable to variation impact assessment as well as variation reduction during circuit design. Systematic models are implemented within a computer aided design (CAD) tool environment to enable automated analysis since the impact of variation is a function of circuit type, performance metric, type of technology, and type of variation source under consideration. The methodology is then applied to study the effects of different variation sources on high performance microprocessor circuit designs for the various performance metrics. The impact of variation is also projected as technology is scaled to the 50 nm generation. Our results indicate that design margin can be tightened significantly if systematic variation models are used for circuit simulation, especially with technology scaling. Thesis Supervisor: Duane S. Boning Title: Associate Professor of Electrical Engineering and Computer Science